********** Mapped Logic ********** |
A <= ((NOT cnt_low2 AND B)
OR (NOT cnt_low1 AND cnt_low2 AND NOT E) OR (NOT cnt_low3 AND NOT B AND E AND NOT XLXI_38/T2/XLXI_38/T2_D2)); |
B <= ((cnt_low1 AND cnt_low0 AND NOT F)
OR (cnt_low1 AND cnt_low3 AND cnt_low2) OR (cnt_low1 AND NOT cnt_low3 AND NOT F) OR (cnt_low0 AND NOT cnt_low3 AND NOT F) OR (NOT cnt_low0 AND cnt_low3 AND cnt_low2)); |
C <= ((cnt_low1 AND cnt_low3 AND cnt_low2)
OR (NOT cnt_low0 AND cnt_low3 AND cnt_low2) OR (cnt_low1 AND NOT cnt_low0 AND NOT cnt_low3 AND NOT cnt_low2)); |
D <= ((cnt_low2 AND XLXI_38/T2/XLXI_38/T2_D2)
OR (NOT cnt_low2 AND B AND E) OR (cnt_low1 AND NOT cnt_low0 AND cnt_low3 AND NOT cnt_low2) OR (NOT cnt_low3 AND NOT B AND E AND NOT XLXI_38/T2/XLXI_38/T2_D2)); |
DP <= '0'; |
E <= ((cnt_low1 AND cnt_low0 AND NOT cnt_low3)
OR (NOT cnt_low1 AND cnt_low0 AND NOT cnt_low2) OR (NOT cnt_low1 AND NOT cnt_low3 AND cnt_low2)); |
FTCPE_EN_DISP0: FTCPE port map (EN_DISP(0),EN_DISP_T(0),CLK_FAST,NOT TASTER_RES,'0');
EN_DISP_T(0) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND XLXI_18/Q(7) AND cnt_low3 AND cnt_low2 AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7) AND XLXI_38/T2/XLXI_38/T2_D2); |
FDCPE_EN_DISP1: FDCPE port map (EN_DISP(1),EN_DISP_D(1),CLK_FAST,'0',NOT TASTER_RES);
EN_DISP_D(1) <= EN_DISP(0) XOR EN_DISP_D(1) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND XLXI_18/Q(7) AND cnt_low3 AND cnt_low2 AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7) AND XLXI_38/T2/XLXI_38/T2_D2); |
F <= ((cnt_low1 AND NOT cnt_low3 AND NOT cnt_low2)
OR (NOT cnt_low1 AND cnt_low2 AND NOT E) OR (NOT cnt_low3 AND NOT cnt_low2 AND E) OR (NOT cnt_low3 AND E AND XLXI_38/T2/XLXI_38/T2_D2)); |
G <= ((NOT cnt_low1 AND NOT cnt_low3 AND NOT cnt_low2)
OR (NOT cnt_low3 AND cnt_low2 AND XLXI_38/T2/XLXI_38/T2_D2)); |
FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),CLK_FAST,'0','0');
LED_D(0) <= ((TASTER_RES AND NOT LED(0) AND NOT cnt_low0/cnt_low0_CE) OR (TASTER_RES AND NOT LED(3) AND cnt_low0/cnt_low0_CE)); |
FDCPE_LED1: FDCPE port map (LED(1),LED_D(1),CLK_FAST,'0','0');
LED_D(1) <= ((TASTER_RES AND NOT LED(0) AND cnt_low0/cnt_low0_CE) OR (TASTER_RES AND NOT LED(1) AND NOT cnt_low0/cnt_low0_CE)); |
FDCPE_LED2: FDCPE port map (LED(2),LED_D(2),CLK_FAST,'0','0');
LED_D(2) <= ((TASTER_RES AND NOT LED(1) AND cnt_low0/cnt_low0_CE) OR (TASTER_RES AND NOT LED(2) AND NOT cnt_low0/cnt_low0_CE)); |
FDCPE_LED3: FDCPE port map (LED(3),LED_D(3),CLK_FAST,'0','0');
LED_D(3) <= ((TASTER_RES AND LED(2) AND cnt_low0/cnt_low0_CE) OR (TASTER_RES AND LED(3) AND NOT cnt_low0/cnt_low0_CE)); |
FTCPE_XLXI_16/Q0: FTCPE port map (XLXI_16/Q(0),'1',CLK_FAST,NOT TASTER_RES,'0'); |
FTCPE_XLXI_16/Q1: FTCPE port map (XLXI_16/Q(1),XLXI_16/Q(0),CLK_FAST,NOT TASTER_RES,'0'); |
FTCPE_XLXI_16/Q2: FTCPE port map (XLXI_16/Q(2),XLXI_16/Q_T(2),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(2) <= (XLXI_16/Q(0) AND XLXI_16/Q(1)); |
FTCPE_XLXI_16/Q3: FTCPE port map (XLXI_16/Q(3),XLXI_16/Q_T(3),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(3) <= (XLXI_16/Q(0) AND XLXI_16/Q(1) AND XLXI_16/Q(2)); |
FTCPE_XLXI_16/Q4: FTCPE port map (XLXI_16/Q(4),XLXI_16/Q_T(4),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(4) <= (XLXI_16/Q(0) AND XLXI_16/Q(1) AND XLXI_16/Q(2) AND XLXI_16/Q(3)); |
FTCPE_XLXI_16/Q5: FTCPE port map (XLXI_16/Q(5),XLXI_16/Q_T(5),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(5) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(2) AND XLXI_16/Q(3)); |
FTCPE_XLXI_16/Q6: FTCPE port map (XLXI_16/Q(6),XLXI_16/Q_T(6),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(6) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(3)); |
FTCPE_XLXI_16/Q7: FTCPE port map (XLXI_16/Q(7),XLXI_16/Q_T(7),CLK_FAST,NOT TASTER_RES,'0');
XLXI_16/Q_T(7) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3)); |
FTCPE_XLXI_18/Q0: FTCPE port map (XLXI_18/Q(0),'1',CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(0));
XLXI_18/Q_CE(0) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_XLXI_18/Q1: FTCPE port map (XLXI_18/Q(1),XLXI_18/Q(0),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(1));
XLXI_18/Q_CE(1) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_XLXI_18/Q2: FTCPE port map (XLXI_18/Q(2),XLXI_18/Q_T(2),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(2));
XLXI_18/Q_T(2) <= (XLXI_18/Q(0) AND XLXI_18/Q(1)); XLXI_18/Q_CE(2) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_XLXI_18/Q3: FTCPE port map (XLXI_18/Q(3),XLXI_18/Q_T(3),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(3));
XLXI_18/Q_T(3) <= (XLXI_18/Q(0) AND XLXI_18/Q(1) AND XLXI_18/Q(2)); XLXI_18/Q_CE(3) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_XLXI_18/Q4: FTCPE port map (XLXI_18/Q(4),XLXI_18/Q_T(4),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(4));
XLXI_18/Q_T(4) <= (XLXI_18/Q(0) AND XLXI_18/Q(1) AND XLXI_18/Q(2) AND XLXI_18/Q(3)); XLXI_18/Q_CE(4) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_XLXI_18/Q5: FTCPE port map (XLXI_18/Q(5),XLXI_18/Q_T(5),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(5));
XLXI_18/Q_T(5) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(2) AND XLXI_18/Q(3)); XLXI_18/Q_CE(5) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_XLXI_18/Q6: FTCPE port map (XLXI_18/Q(6),XLXI_18/Q_T(6),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(6));
XLXI_18/Q_T(6) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(3)); XLXI_18/Q_CE(6) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_XLXI_18/Q7: FTCPE port map (XLXI_18/Q(7),XLXI_18/Q_T(7),CLK_FAST,NOT TASTER_RES,'0',XLXI_18/Q_CE(7));
XLXI_18/Q_T(7) <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3)); XLXI_18/Q_CE(7) <= (XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
XLXI_38/T2/XLXI_38/T2_D2 <= (cnt_low1 AND cnt_low0); |
FTCPE_cnt_low0: FTCPE port map (cnt_low0,'1',CLK_FAST,'0','0',cnt_low0_CE);
cnt_low0_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
cnt_low0/cnt_low0_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND
XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_cnt_low1: FTCPE port map (cnt_low1,cnt_low0,CLK_FAST,'0','0',cnt_low1_CE);
cnt_low1_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_cnt_low2: FTCPE port map (cnt_low2,XLXI_38/T2/XLXI_38/T2_D2,CLK_FAST,'0','0',cnt_low2_CE);
cnt_low2_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
FTCPE_cnt_low3: FTCPE port map (cnt_low3,cnt_low3_T,CLK_FAST,'0','0',cnt_low3_CE);
cnt_low3_T <= (cnt_low2 AND XLXI_38/T2/XLXI_38/T2_D2); cnt_low3_CE <= (XLXI_18/Q(0) AND XLXI_18/Q(4) AND XLXI_18/Q(1) AND XLXI_18/Q(5) AND XLXI_18/Q(2) AND XLXI_18/Q(6) AND XLXI_18/Q(3) AND XLXI_18/Q(7) AND XLXI_16/Q(0) AND XLXI_16/Q(4) AND XLXI_16/Q(1) AND XLXI_16/Q(5) AND XLXI_16/Q(2) AND XLXI_16/Q(6) AND XLXI_16/Q(3) AND XLXI_16/Q(7)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |